1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory such as flash memory, and more particularly, to a nonvolatile memory that is able to perform write (program and erase) and read operations at the same time.
2. Description of the Related Art
Flash memory that uses semiconductor nonvolatile memory is widely used in mobile information terminals, mobile phones and the like because stored data is not lost when the power is off. This nonvolatile memory stores data by setting the gate voltage/drain current characteristic of the transistor at different levels, depending on whether or not the charge is stored in the floating gate or trap gate of a transistor which is formed on the surface of the semiconductor substrate.
In a data write operation this nonvolatile memory comprises a program operation to inject a charge into the floating gate or trap gate and raise the transistor's threshold voltage, and conversely an erase operation to extract the charge and lower the transistor's threshold voltage. The nonvolatile memory, by applying applies to the gate a voltage which is intermediate to the above two threshold voltages, reads the written data according to the value of the drain current flowing in the cell transistor.
Consequently, in a read operation, a prescribed read voltage is applied to the gates of a core cell transistor and a reference cell transistor, and the difference in the voltage level corresponding to the drain current flowing to both transistors is detected by a sense amplifier. A charge is fed into a reference transistor so that the cell transistor has the intermediate threshold voltage between data “1” and “0”. Then, when applying the read voltage to both transistors, data can be detected according to whether the drain current of the core cell transistor is higher or lower than the drain current of the reference cell transistor.
Further, in a write operation, when programming from a data “1” condition at a low threshold voltage to a data “0” condition at a high threshold voltage by injecting a charge, a program verify is performed to determine whether or not the threshold voltage of the cell transistor has become sufficiently high. This program verify is a read operation using a reference cell transistor for programming. In other words, in this operation, program verify voltage is applied to both the reference cell transistor for programming and the core cell transistor, and the difference in the voltage level corresponding to the drain currents of both transistors is detected by the sense amplifier.
Further, in a write operation, when erasure is carried out from a data “0” condition at a high threshold voltage to a data “1” condition at a low threshold voltage by extracting a charge, an erase verify is performed to determine whether or not the threshold voltage of the cell transistor has become sufficiently low. This erase verify is also a read operation using a reference cell transistor for erasure. In other words, in this operation, erase verify voltage is applied to both the reference cell transistor for erasure and the core cell transistor, and the difference in voltage level corresponding to the drain currents of both transistors is detected by the sense amplifier.
In flash memory that uses conventional nonvolatile memory, performing a read operation at the same time as a write operation is not permitted. Therefore, a read operation request made during programming or erasure is denied. However, if a read request is made during sector erasure, as an exception, a special mode is sometimes installed that allows the erase operation to be interrupted and the read request to be accepted. Even in such a case, the erase operation and the read operation are not performed simultaneously.
However, flash memory that is able to accept a read operation during a write operation to a cell inside a chip, and perform read operations and write operations at the same time, has been proposed. For example, a construction exists whereby a plurality of memory banks are provided in the memory core of a chip, a memory cell array and row/column decoders are provided in each memory bank, and write operations and read operations are controlled for each bank. In such a construction, when one memory bank is performing a write operation, another memory bank can perform a read operation.
However, the inventors of the present invention have discovered that in this kind of flash memory that performs write operations and read operations at the same time, due to operations accompanying the read operation which use a large electric current, there is the possibility of a malfunction occurring in the verify operation for the write operation.
FIG. 1 is a schematic circuit diagram of a core cell transistor, a reference cell transistor and a sense amplifier. Further, FIG. 2 is a view explaining the erase verify and the program verify.
As shown in FIG. 1, in the read verify circuit and the write verify circuit, a current path of a core cell transistor C-CEL and a current path of a reference cell transistor Ref-CEL are formed between power supply pads 10 and 12 for the power supply Vcc and the ground Vss, provided inside the chip. The difference in voltage between a node N1 and a node N2 in these current paths is detected by a sense amplifier 14. In other words, the same voltage is applied to the gates WLc and WLref of both cell transistors, and voltage is generated in the nodes N1 and N2 by the drain current flowing to the core cell transistor C-CEL and the drain current flowing to the reference cell transistor Ref-CEL. Then, the difference in voltage of the nodes N1 and N2 is detected by the sense amplifier 14.
Further, inside the current path of the core cell transistor C-CEL, parasite resistance and capacity, and other circuit resistance and capacity RCa-c and RCb-c exist. Similarly, inside the current path of the reference cell transistor Ref-CEL, parasite resistance and capacity, and other circuit resistance and capacity RCa-ref and RCb-ref exist. These resistance and capacity values differ depending on the position of the cell transistor in relation to the power supply wiring and ground wiring inside the chip.
The graph in FIG. 2 shows the gate voltage Vg of the cell transistor on the horizontal axis and the drain current Id on the vertical axis. The reference cell transistor Ref-CEL contains: a read verify transistor having a read verify gate voltage/drain current characteristic RV; a program verify transistor having a program verify gate voltage/drain current characteristic PRV; and an erase verify transistor having an erase verify gate voltage/drain current characteristic ERV. A charge is fed into the floating gate of each of these transistors so as to have the corresponding characteristic.
In read operations, the currents of the core cell transistor C-CEL and the read verify reference cell transistor Ref-CEL are compared, and if the core cell transistor is in a programming state of data “0”, the drain current becomes smaller than the reference, whereas if the core cell transistor is in an erasure state of data “1”, the drain current becomes larger than the reference.
In a program operation that injects a charge into the floating gate of the core cell transistor to change from a data “1” state to a data “0” state, whether or not the characteristic of the core cell transistor during programming C-CEL(P), shown in the drawing by a dotted line, has exceeded the program verify characteristic PRV and moved to the right-hand side of the drawing is detected by comparing the voltage of nodes N1 and N2, which depend on the drain current.
In addition, in an erase operation that extracts a charge from the floating gate of the core cell transistor to change from a data “0” state to a data “1” state, whether or not the characteristic of the core cell transistor during erasure C-CEL(E), shown in the drawing by a dotted line, has exceeded the erase verify characteristic ERV and moved to the left-hand side of the drawing is detected by comparing the voltage of nodes N1 and N2, which depend on the drain current.
However, depending on the location of the core cell transistor C-CEL that is subject to read or verify operations, the resistance/capacity values RCa-c and RCb-c in the current path become bigger or smaller than the corresponding values RCa-ref and RCb-ref in the reference transistor. Then, when a large current is used in a decode operation, output operation or the like during a read operation, variation occurs in the power supply Vcc and Vss levels. Such a power supply variation ordinarily occurs in operations using a large current, but when the above-mentioned resistance/capacity values of both the current paths are different, the effect of the power supply variation on each node N1 and N2 is different, leading to a malfunction in the verify operation.
For example, a malfunction during erase verify will now be explained. Suppose that in terms of the resistance/capacity values of the current path of the power supply Vcc, the core is smaller than the reference (RCa-c<RCa-ref). In this case, if the level of the power supply Vcc temporarily declines due to the use of a large current during a read operation that is in progress at the same time, the node N1, which has a small resistance/capacity value, is more likely to follow the decline of the power supply Vcc than the node N2, and the potential of the node N1 will further decline. For the sense amplifier 14, the reduction in the electric potential of the node N1 means that the drain current of the core cell transistor C-CEL becomes larger. As shown by the arrow C1 in FIG. 2, this phenomenon means that despite the fact that the characteristic of the core cell transistor C-CEL(E) is in a condition of incomplete erasure, positioned on the right-hand side of the characteristic of the erase verify reference cell transistor ERV, the sense amplifier 14 detects it as though it had moved to the left-hand side of the characteristic ERV.
Further, suppose that in terms of the resistance/capacity values of the ground current path, the core is larger than the reference (RCb-c>RCb-ref). In this case, if the ground potential Vss rises due to a read operation that is in progress at the same time, the node N2, which has a small resistance/capacity value, is more likely to follow the rise of the ground potential Vss than the node N1, and the potential of the node N2 will rise further. For the sense amplifier 14, the rise in the electric potential of the node N2 means that the drain current of the reference cell transistor Ref-CEL becomes smaller. Consequently, as shown by the arrow C2 in FIG. 2, this phenomenon means that despite the fact that it is in a condition of incomplete erasure, the sense amplifier 14 detects it as though the characteristic of the erase verify cell transistor ERV had moved to the right-hand side of the characteristic of the core cell transistor C-CEL(E).
In either of the above cases, despite the fact that erasure is incomplete, the erase verify decision, when a large current has been used by a read operation that is in simultaneous progress, shows erasure as being complete.
A similar mistaken verify decision is triggered in program verify. That is, when RCa-c>RCa-ref, if the power supply Vcc declines due to a read operation, the node N2 follows that power supply reduction even more such that N1>N2, and the drain current Id of the reference cell transistor Ref-CEL becomes even greater, meaning that a characteristic variation has arisen, as shown by the arrow C3 in the drawing.
Further, when RCb-c<RCb-ref, if the ground Vss rises due to a read operation, the node N1 follows this ground rise even more such that N1>N2, and the drain current ID of the core cell transistor C-CEL becomes even smaller, meaning that a characteristic variation has arisen, as shown by the arrow C4 in the drawing.
Accordingly, in program verify, despite the fact that programming is incomplete, the program verify decision, when a large current has been used by a read operation that is in is simultaneous progress, shows programming as being complete.
As described above, mistakes occur in the erase verify and program verify decision results accompanying the use of a large current when a read operation is in simultaneous progress.